There is a constant drive within the semiconductor industry to increase the performance and reduce the cost of semiconductor devices, such as photodetectors, diodes, light-emitting diodes, transistors, latches, and many other semiconductor devices. This drive has resulted in continual demands for integrating one type of semiconductor devices into another semiconductor process.
For example in photodetectors that are comprised of an array of p-n junctions or p-i-n structures, it is advantages to make the p-n junctions and/or p-i-n structures with low band-gap materials, such as germanium (Ge) and InGaAs, because the photodetectors are able to detect infrared light. In favor of the cost-efficiency, it is desired to produce a thin film of III-V or other non-silicon materials on low-cost large-size silicon wafers to reduce the cost of high performance III-V devices. It is further desired to integrate non-silicon p-n junctions and/or p-i-n structures (e.g. Ge or InGaAs based) into a silicon process such that other circuitry in a system, such as a photodetector, can be fabricated using a standard silicon process, such as a standard CMOS (complementary-metal-oxide-semiconductor) process. It is also desirable to fabricate the non-silicon devices and silicon CMOS in a co-planar manner, so that the interconnection and integration of the whole system can be conducted in a manner compatible with standard and low-cost CMOS process. Further, it is desirable to increase a size of non-silicon regions configured to output electrons generated by light absorption therein.